Design verification is a common process for testing an integrated circuit, board, or system-level architecture, to confirm it complies with the requirements defined by the specification of the architecture for that device. Design verification for a device under test (DUT) may be performed on the actual device, or on a simulation model of the device.
Verifying a design using a simulation model of the device involves using hardware description languages (HDL) such as Verilog and VHDL. These languages are designed to describe hardware at high levels of abstraction. The generated simulated model of the tested device can receive input stimuli in the form of test vectors, which are a string of binary values applied to the input of a circuit. The simulated model then produces results, which are checked against the expected results for the particular design of the device.
However, HDLs are not designed for actual verification. Therefore, the verification engineer has to write additional programming code in order to interface with the models described by these hardware description languages in order to perform design verification of the device.
When verifying an actual, manufactured device (or a similar device implemented in a fast technology such as a field programmable gate array (FPGA)), there is still a need to inject input stimuli, similar to the stimuli used for verifying a simulation.